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TCM8240MD Ver 1.2
TOSHIBA C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TCM8240MD
TENTATIVE
1.3 Mega pixel sensor chip
Ver 1.2
13/Nov/04
TCM8240MD is an area color image sensor , at 1.3 Mega-pixels of array resolution (1300x 1040) , incorporating a camera signal processor . The optical format is 1/3.3 inch, of which small size is suitable for built-in camera module application. Use of the CMOS process makes possible low power consumption operations. This sensor provides superb picture quality thanks to Toshiba's advanced sensor technology and Toshiba's sophisticated signal processing technology. Features 1. General * * * * * * * * * * * * Large flexibility in external clock frequency range by PLL operation (JPEG is not available in case of w/o PLL operation) Frame rate : up to 15 fps for every resolution Output data rate reduction for full 1.3 Mega resolution by JPEG compression Dual power supply : Either 2.5+/-0.2V or 2.8 +/- 0.2 V, and 1.6+/-0.1V Operation temperature : -20 to + 60 degree C Storage temperature : -30 to +85 degree C Optical size Effective pixel numbers Output pixel number Pixel pitch Image size Color filter : 1/3.3 inch optical format : 1300(H) x 1040(V) : 1280(H) x1024 (V) maximum : 3.3um(H)x3.3um(V) (square pixel) : 4.29 mm(H) x 3.43mm(V) : Primary color filter, Bayer arrangement
2. Sensor
3. Camera signal processing * Digital output mode Output terminals: 8bit parallel data output along with DCLK, HBLK, and VBLK (1) YUV=4:2:2 or RGB=5:6:5 data (multiplexed 8bit parallel output ) (2) JPEG encoded data (8 bit parallel) for full 1.3 Mega data * Multi-step digital zoom for downsized VGA, QVGA, QQVGA, CIF, QCIF and subQCIF * Vertical and horizontal flip * ALC ( automatic luminance level control) with fluorescent flicker-less operation * AWB ( automatic white balance) * Automatic blemish detection and correction * Strobe pulse for flash trigger
*oe TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or
jail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating range as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. *oe products described in this document are subject to foreign exchange and foreign trade control laws. The *oe The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. N license is granted by o implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. *oe information contained herein is subject to change without notice. The
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TCM8240MD Ver 1.2
CHANGE HISTORY
Specifications draft Specifications draft Specifications draft Specifications draft V0.4 V1.0 V1.1 V1.2 December 9, `03 October 14, `04 October 14, `04 November 13,`04
LIST OF ABBREVIATION
VGA CIF CDS AGC ADC TG SG PLL VCO AWB OB ALC SOI EOI MCU DQT DHT SOF SOS DRI Video Graphic Array Common Intermediate Format Correlated Double Sampling Automatic Gain Control Analog to Digital Converter Timing Generator Sync Signal Generator Phase Locked Loop Voltage Controlled Oscillator Automatic white Balance Optical black Automatic Luminance level control Start of Image ( in JPEG data stream) End of Image ( in JPEG data stream) Minimum Coded Unit Define Quantization table Define Huffman Table Start of Frame Start of Scan Define Restart Interval
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TCM8240MD Ver 1.2
BLOCK DIAGRAM
1.3 Mega sensor chip
JPEG compression Image Section CDS/AGC Signal Processing Digital zoom
ADC
Selector
TG
SG
PLL/VCO
IIC bus I/F
2
3
8
GND
PVDD
RESET DVDD SDA EXTCLK HBLK, VBLK STROBE DOUT0 IOVDD SCL DCLK to DOUT7
Host Engine
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' 9' ' *1' 6' $ *1' 6& / 5 ( 6( 7
PIN DESCRIPTION
' &/ .
*1'
' 2 87
' 2 87
' 2 87
' 2 87
TCM8240MD Ver 1.2
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TCM8240MD Ver 1.2
I/O INTERNAL CIRCUITS
NAME I/O INTERFACE CIRCUIT
AVDD AVDD
AVDD
RESET
GND
I
GND
GND
AVDD
SCL
I
GND
GND
AVDD
SDA
I/O
GND
GND
GND
AVDD
AVDD
AVDD
EXTCLK
I
GND
AVDD
GND
GND
GND
AVDD
AVDD
DOUT0 to DOUT7, HBLK, VBLK, DCLK,STROBE
O
GND
GND
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TCM8240MD Ver 1.2
CONTROL I/F
TCM8240MD control interface configuration is based on fast mode IIC bus. Register setting can be changed via IIC bus.
Write mode
S Slave Address 0 A Sub Address A MSB 7bit MSB 8bit DATA1 MSB 8bit A ----DATAn 8bit AP
Read mode
S Slave Address MSB 7bit 0 A Sub Address A S MSB 8bit Slave Address MSB 7bit 1A DATA1 MSB 8bit A - - - - - DATAn 8bit AP
: Host Command
Camera
S : Start condition , P : End condition , A : Acknowledge, A : not Acknowledge
Start condition , End condition
Bit Transfer
SDA SCL S Start condition
Acknowledge
SDA SCL P End conditon
data line stable of data allowed change data;valid HiZ NACK HiZ 8 9
Not Acknowledge
SDA trancemitter from SDA reciver from SCL master from S 1
Slave address
A6 A5 A4 A3 A2 A1 A0 R/W 0 1 1 1 1 0 1 1/0 7bit Slave address is used.
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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TCM8240MD Ver 1.2
INTERNAL REGISTER
Address Address Data Dec Hex (D7) (D6) 0 00 1 01 2 02 STANDBYSW SRST 3 03 4 04 DOUTOFF JPEGON FRM_SPD[1:0] 5 05 6 06 UDINV 7 07 8 08 9 09 10 0A 11 0B 12 0C 13 0D 14 0E 15 0F 16 10 17 11 18 12 19 13 20 14 21 15 22 16 23 17 24 18 25 19 26 1A H_COUNT[7:0] 27 1B V_COUNT[3:0] 28 1C 29 1D 30 1E SP_COUNT[7:0] 31 1F 32 20 33 21 34 22 STSET_SW STSET_POL 35 23 36 24 37 25 38 26 39 27 40 28 41 29 42 2A 43 2B 44 2C FRAME_LV[7:0] 45 2D CB_MODE[2:0] 46 2E DINSW 47 2F 48 30 49 31 APCSW 50 32 51 33 IDRS[1:0] PPEDR[8:1] 52 34 53 35 PPEDGR[8:1] 54 36 PPEDGB[8:1] 55 37 PPEDB[8:1] 56 38 AGMIN_PPED[8:1] AGMAX_PPED[8:1] 57 39 58 3A 59 3B 60 3C 61 3D PWB_R[7:0] 62 3E 63 3F PWB_GR[7:0]
*m *m *n *n
(D5)
(D4)
(D3)
(D2)
(D1)
(D0)
Initial *m Hex*n 00 00 00 C0 80 40 18 00 08 00 08 36 00 00 AC 00 FA 02 20 B2 33 32 28 00 00 00 B3 B2 A1 00 00 04 73 01 07 F0 5E 10 01 32 40 58 20 10 00 0E 44 00 00 03 FF 00 80 78 78 80 80 80 80 80 80 80 66 80
DCLKPOL PICMODE[1:0]
PLLMODE[3:0] SELRGB
PICSIZ[2:0] LRINV
VSUPCNT[1:0]
H_COUNT[9:8] V_COUNT[9:4] F_COUNT[5:0] SP_COUNT[11:8]
STSET_REG STOUT_POL
ST_MODE[2:0] STOUT_W[1:0]
ST_OUTSIG
FRAME_LV[9:8]
AGMAX_PPED[0] AGMIN_PPED[0] PPEDB[0]
PPEDGB[0]
PPEDGR[0]
PPEDR[0]
The registers of gray mesh (unassigned registers) are not able to read and write via I2C bus. "*" registers are read only. Don't touch TESTMODE registers.
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TCM8240MD Ver 1.2
Address Address Data Dec Hex (D7) (D6) (D5) (D4) PWB_GB[7:0] 64 40 65 41 PWB_B[7:0] 66 42 PWB_BM[1:0] PWB_GBM[1:0] 67 43 LSCSW 68 44 LSC_RG[7:0] LSC_GG[7:0] 69 45 70 46 LSC_BG[7:0] 71 47 HLCC_SW 72 48 ALC_SW F_AUTO_SW F_AUTO_DLY[1:0] 73 49 ALCL[7:0] 74 4A ALC_MODE[4:0] 75 4B ALC_DLY[1:0] ALCH[5:0] 76 4C ALC_DLY[9:2] 77 4D L8P100S[7:0] ALC_SPD[3:0] 78 4E 79 4F L8P120S[7:0] 80 50 ALC_HOLD 81 51 EVS_MIN[7:0] 82 52 EVS_SW[1:0] EVS_CUDSW EVS_MAX[7:0] 83 53 84 54 EVS_MODE[4:0] 85 55 HS_ES_LIM[2:0] 86 56 MES[7:0] 87 57 MES[15:8] LS_ES_LIM[3:0] 88 58 89 59 MDG[7:0] 90 5A AG_MIN[7:0] 91 5B AG_MAX[7:0] 92 5C MAG[7:0] 93 5D ALC_AG_POLE 94 5E ASC_AG[7:0] 95 5F ACDET_SW AC5060HZ ACDET_DLY[1:0] 96 60 97 61 98 62 99 63 100 64 101 65 IDRE_SW APBC_SW PBC_SW[3:0] 102 66 103 67 PBC_MODE[7:0] 104 68 PBC1LV[7:0] 105 69 PBC2LV[7:0] 106 6A PBC3LV[7:0] PBC4LV[7:0] 107 6B 108 6C VDS_HLPFSW[1:0] HDS_VLPFSW[1:0] 109 6D AWB_SW AWB_MODE[1:0] AWB_LOCK 110 6E AWB_WAIT[1:0] YLCUT_SW RGBCUT_SW 111 6F 112 70 113 71 114 72 115 73 116 74 117 75 118 76 119 77 120 78 YLCUT_L[7:0] YLCUT_H[7:0] 121 79 122 7A UVIS_NC[7:0] 123 7B AWB_SSP[7:0] 124 7C AWB_MSP[7:0] 125 7D WBG_SMIN[7:0] WBG_SMAX[7:0] 126 7E 127 7F WBG_MMIN[7:0]
*m *m *n *n
(D3)
(D2)
(D1)
(D0)
Initial *m Hex*n 80 96 41 00 FF FF FF 84 85 50 48 C7 00 EE 14 1C 04 00 20 FF 03 80 3B 01 50 00 3F E7 80 03 00 43 08 08 00 80 00 80 D8 BF 10 10 60 18 02 21 06 00 40 C0 80 80 80 88 10 F0 40 C0 08 FF FF 33 50 20
PWB_GRM[1:0]
PWB_RM[1:0]
ALC_SSW
ALC_CSW[2:0] ALCL[9:8]
L8P100S[11:8] L8P120S[11:8] EVS_MIN[9:8] EVS_MAX[9:8] MHSS[3:0]
MES[17:16]
MAG[9:8] ASC_AG[9:8]
IDRE_CR[1:0]
IDRE_CL[1:0]
AWB_PN[2:0]
The registers of gray mesh (unassigned registers) are not able to read and write via I2C bus. "*" registers are read only. Don't touch TESTMODE registers.
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TCM8240MD Ver 1.2
Address Address Data Dec Hex (D7) (D6) WBG_MMAX[7:0] 128 80 129 81 WB_MRG[7:0] 130 82 WB_MBG[7:0] 131 83 ST_MRG[7:0] 132 84 ST_MBG[7:0] 133 85 134 86 CLM_G[7:0] 135 87 CLM_S[7:0] 136 88 CLM_MIN[7:0] 137 89 CLM_MAX[7:0] YUV_G[7:0] 138 8A 139 8B YUV_S[7:0] 140 8C YUV_MIN[7:0] 141 8D YUV_MAX[7:0] 142 8E 143 8F 144 90 UV_G[7:0] 145 91 UV_S[7:0] 146 92 147 93 CCB_SW 148 94 149 95 SCLPFG[7:0] CBGMIN_L[7:0] 150 96 151 97 CBGMIN_H[7:0] 152 98 CBU_YL[7:0] 153 99 CBD_YL[7:0] 154 9A LCSMODE[3:0] 155 9B 156 9C 157 9D LPFMODE 158 9E LPF_FC[7:0] 159 9F CLM_ANRSW CLM_GC[7:0] 160 A0 161 A1 CLM_RMG[7:0] 162 A2 CLM_RMB[7:0] 163 A3 CLM_GMR[7:0] 164 A4 CLM_GMB[7:0] CLM_BMR[7:0] 165 A5 166 A6 CLM_BMG[7:0] 167 A7 MWB_RG[7:0] 168 A8 MWB_BG[7:0] 169 A9 ABB_SW 170 AA 171 AB 172 AC 173 AD 174 AE 175 AF 176 B0 177 B1 178 B2 R_BKLV[7:0] 179 B3 G_BKLV[7:0] 180 B4 181 B5 182 B6 B_BKLV[7:0] 183 B7 184 B8 GAM_SW[1:0] 185 B9 186 BA 187 BB 188 BC 189 BD 190 BE 191 BF
*m *m *n *n
(D5)
(D4)
(D3)
(D2)
(D1)
(D0)
Initial *m Hex*n 80 40 40 40 40 00 80 80 00 FF 00 00 00 00 80 80 80 80 00 A0 05 80 A0 E0 60 A8 03 60 60 05 80 00 08 80 40 80 80 40 80 80 80 07 80 00 00 00 80 00 00 80 00 08 00 08 00 08 FF 00 00 00 00 00 00 00
RGBLPFSW[3:0]
R_BKLV[11:8] G_BKLV[11:8] B_BKLV[11:8] GAM_SCW[5:0] GAM_SCH[5:0] MCC_RMG[5:0] MCC_RMB[5:0] MCC_GMR[5:0] MCC_GMB[5:0] MCC_BMR[5:0] MCC_BMG[5:0]
The registers of gray mesh (unassigned registers) are not able to read and write via I2C bus. "*" registers are read only. Don't touch TESTMODE registers.
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TCM8240MD Ver 1.2
Address Address Data Dec Hex (D7) (D6) HDCVHSW 192 C0 193 C1 HDCVH_NC[7:0] 194 C2 HDCVH_G[7:0] 195 C3 HDCHSW 196 C4 HDCH_NC[7:0] HDCH_G[7:0] 197 C5 198 C6 HDCMHSW HDCMH_FS[2:0] 199 C7 HDCMH_NC[7:0] 200 C8 HDCMH_G[7:0] VDC_PG[1:0] 201 C9 202 CA VDC_NC[7:0] 203 CB VDC_G[7:0] 204 CC 205 CD HDC_PL[7:0] 206 CE VDC_PL[7:0] 207 CF HDC_MG[7:0] 208 D0 VDC_MG[7:0] 209 D1 210 D2 211 D3 NEPO 212 D4 UV_ACSSW 213 D5 214 D6 215 D7 CONTRAST_Y[7:0] 216 D8 SEPIA 217 D9 218 DA 219 DB BRIGHT_Y[7:0] 220 DC RMYA[6:0] 221 DD RMYG[7:0] 222 DE BMYA[6:0] BMYG[7:0] 223 DF 224 E0 AVGSW 225 E1 ZHCORE[2:0] 226 E2 ZVCORE[2:0] 227 E3 228 E4 229 E5 230 E6 231 E7 232 E8 233 E9 DYQTG[7:0] 234 EA DUVQTG[7:0] 235 EB 236 EC 237 ED 238 EE 239 EF DRI[15:8] 240 F0 241 F1 DRI[7:0] 242 F2 243 F3 244 F4 245 F5 246 F6 ENCDCNT[23:16] 247 F7 ENCDCNT[15:8] 248 F8 ENCDCNT[7:0] 249 F9 250 FA FULL_ERRN ENC_ERRN 251 FB 252 FC 253 FD 254 FE 255 FF
*m *m *n *n
(D5)
(D4)
(D3) HDCVH_PC
(D2)
(D1)
(D0)
Initial *m Hex*n 88 0F 40 08 00 00 08 00 00 08 0F 40 36 60 60 48 60 00 00 38 20 20 20 40 10 10 10 90 40 B6 40 8F 80 88 88 00 80 10 00 00 00 10 10 00 00 00 14 3C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
HDCH_FS[1:0]
HDCH_PC
HDCMH_PC
VDC_PC
Y_MATSW DA_MODE CONTRAST_R[5:0] CONTRAST_G[5:0] CONTRAST_B[5:0] BRIGHT_R[5:0] BRIGHT_G[5:0] BRIGHT_B[5:0]
ZOOMMODE[5:0] ZHDTL[4:0] ZVDTL4:0]
VQTSEL[1:0] VHTSELAC
VHTSELDC
UQTSEL[1:0] UHTSELAC
UHTSELDC
YQTSEL[1:0] YHTSELAC
YHTSELDC
The registers of gray mesh (unassigned registers) are not able to read and write via I2C bus. "*" registers are read only. Don't touch TESTMODE registers.
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TCM8240MD Ver 1.2
OUTLINE OF INTERNAL REGISTER
* Frame rate setting (15ps, 7.5fps ) * Picture size setting of digital output ( 4VGA, SXCA, VGA, QVGA, QQVGA, CIF, QCIF, subQCIF ) * Selection of digital data output format (8bit YUV422, RGB565) * JPEG ON/OFF * Color signal adjustment ( Carrier boost, Linear matrix, YUV matrix, saturation, etc. ) * Luminance signal adjustment ( Contrast, Brightness, Gamma, H,V edge enhancement ) * ALC(Automatic Luminance level Control) ON/OFF * ALC mode setting ( area selection, speed selection, flicker reduction mode setting ) * AWB ON/OFF * Vertical and Horizontal flip * Standby mode setting * Some kinds of correction setting ( Lens shading correction etc. )
8bit parallel image data
YUV mode 2nd 3rd Y0(n) V0(n) Y1(n) V1(n) Y2(n) V2(n) Y3(n) V3(n) Y4(n) V4(n) Y5(n) V5(n) Y6(n) V6(n) Y7(n) V7(n) RGB mode 1st 2nd B0 G3 B1 G4 B2 G5 B3 R0 B4 R1 G0 R2 G1 R3 G2 R4
DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7
1st U0(n) U1(n) U2(n) U3(n) U4(n) U5(n) U6(n) U7(n)
4th Y0(n+1) Y1(n+1) Y2(n+1) Y3(n+1) Y4(n+1) Y5(n+1) Y6(n+1) Y7(n+1)
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TCM8240MD Ver 1.2
DATA OUTPUT TIMING CHART
Timing chart for each output picture size Full Mega output without JPEG
HBLK
VBLK 960 H ( or 1024 H) DATA(D0-D7) 92 H (or 28H )
DCLK Frequency = DSP clock VBLK
HBLK V BLANKING DATA(D0-D7) IMAGE DATA 2560 clocks H BLANKING 224clocks
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TCM8240MD Ver 1.2 VGA ( x1: no zooming)
HBLK
VBLK 959 H DATA(D0-D7) 93 H
DCLK Frequency = 1/2 of DSP clock VBLK
HBLK V BLANKING DATA(D0-D7) IMAGE DATA 1280 clocks H BLANKING 112 clocks + 1H
VGA (at maximum magnification x2)
HBLK
VBLK 480 H DATA(D0-D7) 572 H
DCLK Frequency = 1/2 of DSP clock VBLK
HBLK V BLANKING DATA(D0-D7) IMAGE DATA 1280 clocks H BLANKING 112 clocks
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TCM8240MD Ver 1.2 CIF ( x1: no zooming)
HBLK
VBLK 957 H DATA(D0-D7) 95 H
DCLK Frequency = 1/2 of DSP clock VBLK
HBLK V BLANKING DATA(D0-D7) IMAGE DATA 704 clocks H BLANKING 688 clocks +1H or 3H
CIF (at maximum magnification)
HBLK
VBLK 288 H DATA(D0-D7) 764 H
DCLK Frequency = 1/2 of DSP clock VBLK
HBLK V BLANKING DATA(D0-D7) IMAGE DATA 704 clocks H BLANKING 688 clocks
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TCM8240MD Ver 1.2 QVGA ( x1: no digital zooming)
HBLK
VBLK 956 H DATA(D0-D7) 96 H
DCLK Frequency = 1/4 of DSP clock VBLK
HBLK V BLANKING DATA(D0-D7) IMAGE DATA 640 clocks H BLANKING 56 clocks + 3H
QVGA ( at maximum magnification. X4)
HBLK
VBLK 240 H DATA(D0-D7) 812 H
DCLK Frequency = 1/4 of DSP clock VBLK
HBLK V BLANKING DATA(D0-D7) IMAGE DATA 640 clocks H BLANKING 56 clocks
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TCM8240MD Ver 1.2 QCIF ( x1: no digital zooming)
HBLK
VBLK 954 H DATA(D0-D7) 98 H
DCLK Frequency = 1/4 of DSP clock VBLK
HBLK V BLANKING DATA(D0-D7) IMAGE DATA 352 clocks H BLANKING 344 clocks + 3H or 7H
QCIF ( at maximum magnification : x 6.67)
HBLK
VBLK 144 H DATA(D0-D7) 908 H
DCLK Frequency = 1/4 of DSP clock VBLK
HBLK V BLANKING DATA(D0-D7) IMAGE DATA 352 clocks H BLANKING 344 clocks
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TCM8240MD Ver 1.2 QQVGA (x1: no digital zooming)
HBLK
VBLK 952 H DATA(D0-D7) 100 H
DCLK Frequency = 1/4 of DSP clock VBLK
HBLK V BLANKING DATA(D0-D7) IMAGE DATA 320 clocks H BLANKING 376 clocks +7H
QQVGA ( at maximum magnification: x 8 )
HBLK
VBLK 120 H DATA(D0-D7) 932 H
DCLK Frequency = 1/4 of DSP clock VBLK
HBLK V BLANKING DATA(D0-D7) IMAGE DATA 320 clocks H BLANKING 376 clocks
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TCM8240MD Ver 1.2 subQCIF ( x1: no digital zooming)
HBLK
VBLK 950 H DATA(D0-D7) 102 H
DCLK Frequency = 1/4 of DSP clock VBLK
HBLK V BLANKING DATA(D0-D7) IMAGE DATA 256 clocks H BLANKING 440 clocks + 9H
subQCIF ( at maximum magnification: x 10)
HBLK
VBLK 96 H DATA(D0-D7) 956 H
DCLK Frequency = 1/4 of DSP clock VBLK
HBLK V BLANKING DATA(D0-D7) IMAGE DATA 256 clocks H BLANKING 440 clocks
Remark: the downsized picture has generally intermittent output by line, but in a horizontal line the image data are put together to form a continuous stream.
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TCM8240MD Ver 1.2 JPEG encoded full Mega
VBLK
HBLK
D0 - D7
SOI
EOI
SOI
JPEG encoded data contains the standardized marker codes such as SOI and EOI. HBLK is set to high when JPEG data are output. The data length of one packet is multiple of MCU. It is using 8 lines buffer memories (FIFO) when JPEG encoding. It is limited for the writing not to surpass the reading because the writing speed is earlier than the reading speed. It is not limitation for low level period of HBLK. Also, following register setting, it is available to output by 4 bytes unit (multiple). HBLK is for data enable and high level period continues clock of 4 multiples. It is not limitation for low level period of HBLK. Also, when the JPEG data of 1V period is not 4 multiples, the data of address A5h makes to add after address FFh and address D9h because it needs to become 4 multiples. * Setting of reading 4 bytes unit Address E6h D[3] J4BYTESW
"High" setting: JPEG output by 4 bytes unit
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TCM8240MD Ver 1.2
JPEG DATA FORMAT
Block diagram
YUV422 MCU MCU
8 lines FIFO Sensor/DSP 8 lines FIFO JPEG core
2MCU FIFO
JPEG control
JPEG data structure
The following figure shows JPEG data structure. Data stream
SOI
DQT
SOF
DHT
SOS
Image
EOI
SOI DQT SOF DHT SOS Image data EOI(16bit)
Marker code 16'hFFD8 Marker code 16'hFFDB Marker code 16'hFFC0 Marker code 16'hFFC4 Marker code 16'hFFDA MCU1*MCU10240 *i 1280 x 1024 pixels) for Marker code 16'hFFD9
The following tables show the data structure of DQT,SOF,DHT and SOS respectively. The host can adjust the picture quality mode (namely compression ratio) by sending a specific quantization table or by sending Q table gain via IIC bus. The JPEG encoded data are once stored an internal FIFO memory before outputting. When data overflow in FIFO happens due to locally increased JPEG data ( locally very low compression) , data transmission is stopped after FE code addition and an error flag is written in the register table. After the host accesses the error flag register, the error flag is automatically reset.
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TCM8240MD Ver 1.2
DQT structure
+00 +01 +02 +04 +05
+45 +46
+86 +87
Code (Hex) FF DB 00 C5 00 : : : : : 01 : : : : : 02 : : : : :
Meaning Marker Prefix DQT Length of field 2+(1+64)*3=197 (Byte) Y: Pq=0, Nq=0 Quantization table Y*F Q0 : : : Quantization table Y*F Q63 U: Pq=0, Nq=1 Quantization table U*F Q0 : : : Quantization table U*F Q63 V: Pq=0, Nq=0 Quantization table V*F Q0 : : : Quantization table V*F Q63
SOF structure
Code (Hex) FF C0 00 C5 00 XX YY WW ZZ 03 01 21 00 02 11 01 03 11 02 Meaning Marker Prefix SOF Length of field 2+1+2+1+2*3=17 (Byte) Data precision (bits) vertical lines XXYY ( Hex) lines horizontal lines WWZZ ( Hex) lines Components Components number (1:Y) H0=2, V0=1(4:2:2) Quantization designation Components number (2:U) H1=1, V1=1 Quantization designation Components number (2:U) H2=1,V2=1 Quantization designation
+00 +01 +02 +03 +04 +05 +06 +07 +08 +09 +0A +0B +0C +0D +0E +0F +10 +11 +13
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TCM8240MD Ver 1.2
DHT structure
Code (Hex) FF C4 01 A2 00 Meaning Marker Prefix DHT Length of field 2+(1+16+12+1+16+162)*2=418 (Byte) Table number Y-DC : 00 DHT parameter 10 Table number Y-AC : 10 DHT parameter 01 Table number C-DC : 01 DHT parameter 11 Table number C-AC : 11 DHT parameter 00 Table number Y-DC : 00 DHT parameter 10 Table number Y-AC : 10 DHT parameter 01 Table number C-DC : 01 DHT parameter 11 Table number C-AC : 11 DHT parameter
+00 +01 +02 +04
Remark : the current JPEG logic core outputs two sets of Huffmann table. SOS structure
+00 +01 +02 +04 +05 +06 +07 +08 +09 +0A +0B +0C +0D
Code (Hex) FF DA 00 0C 03 01 00 02 11 03 11 00 3F 00
Meaning Marker Prefix SOS Length of field 2+1+3*2+3=12 (Byte) Components in scan Components selector Y:01 Huffmann table selector Y:00 Components selector U:02 Huffmann table selector C:11 Components selector V:03 Huffmann table selector C:11 Scan start position in block Scan end position in block Succesive approximation Bit position
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TCM8240MD Ver 1.2
OPERATING FLOW
The sensor chip supports the operating mode and the standby mode as shown in the following figure. power management
In power off mode, the output pins are not in High-Z status.
Power off mode
AVDD ON OFF OFF
DVDD
ON
OFF
OFF
EXTCLK
ON
OFF
OFF
RESET
ON
OFF IIC command Standby in
OFF
Operating mode
Standby out
Standby mode
In standby mode, the latest status of output pins is restored. If the host sends "Lowfixed" command before sleep command, all the output pins are set to "Low".
Powering order and timing margin are shown in the following figure. Timing description in power sequence
>= 0 sec ( no order reverse. Sametime is OK)
AVDD
DVDD
>= 0 msec ( no order reverse. Sametime is OK)
>= 0 msec ( no order reverse. Sametime is OK)
EXTCLK
>= 0 msec ( no order reverse. Sametime is OK)
>= 0 msec ( no order reverse. Sametime is OK)
>= 0 msec >1 msec
RESET
353 msec Effective data period for stable VCO
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TCM8240MD Ver 1.2
When 1.6V power line is higher than 2.5V power line, the current is provided from 1.6V power line to 2.5V power line via internal protection diode. When 2.5V power line is open, the current is provided to 2.5V power line from 1.6V power line via internal protection diode. Then 1V is provided at 2.5V power line and 1.6V is provided at 1.6V power line. When 2.5V power line is connected to GND, 1.6V power line is shorted to GND at low impedance. These conditions can not be guaranteed and it need to consideration to design.
Acceptable period for command setting
The following figure shows the command acceptable period. In general the status of the next frame data is immediately reflected by the command, but in case of the commands dealing with sensor operation such as exposure time setting, the frame after next is reflected. Register setting is available between top of full mega pixel image and end of image. The minimum period happens in case of sub QCIF maximum zooming. The command acceptable period after VBLK turns high is 36 msec for 15 fps operation and 71.5 msec for 7.5fps.
Maximum case VBLK DOUT (Full mega) Command acccept
1024 or 960 line
In case of 15fps, 65ms In case of 7.5fps, 130ms
Minimum case VBLK DOUT (QCIF-Zoom) Command accept
96 line
In case of 15fps, 36ms In case of 7.5fps, 71.5ms
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TCM8240MD Ver 1.2
MAXIMUM RATING
CHARACTERISTICS Power supply voltage Input voltage Storage tempature SYMBOL PVDD (AVDD25), IOVDD (IOVDD25, IOAVD25) DVDD (AVDD15, DVDD15) VIN Tstg RATING -0.3 to 3.6 -0.3 to 3.0 -0.3 to VDD+0.3 -30 to 85 UNITS V V V Degree C
RECOMMENDED OPERATION CONDITION
Note; * If using 2.5V operation, must input setting command. (Default setting is 2.8V operation.)
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TCM8240MD Ver 1.2
ELECTRICAL CHACTERISTICS
DC Characteristics (Ta=25 degree C, PVDD=IOVDD=2.8V, DVDD=1.6V)
1. POWER CONSUMPTION (Ta=25 degree C, PVDD=IOVDD=2.5V, DVDD=1.6V, 15fps operation, dark condition)
ITEM IOVDD, PVDD DVDD POWER * IOVDD, PVDD DVDD IOVDD, PVDD DVDD CONDITION Normal mode Output data: YUV Output data: JPEG * MIN TYP 20 100 10 90 MAX 30 150 15 140 11 5100 UNITS mA mA mA mA A A
Standby modeTa=60 degree C
Note; * Measurement condition: Machbeth chart(full) * JPEG table is standard.
2. EXTCLK
ITEM HIGH level input voltage LOW level input voltage Rectanglar shape HIGH level input current LOW level input current DUTY * SYMBOL VIH EXTCLK VIL EXTCLK IIH EXTCLK IIL EXTCLK CONDITION VIN=IOVDD VIN=GND MIN IOVDD x 0.8 -10 -10 45/55 TYP MAX IOVDD x 0.2 10 10 55/45 UNITS V V A A %
Note; * Duty is referred to 50% level of input EXTCLK.
3. SCL, SDA
SCL ITEM HIGH level input voltage LOW level input voltage HIGH level input voltage SDA LOW level input voltage LOW level output voltage SYMBOL VIH SCL VIL SCL V IH SDA V IL SDA VOL SDA CONDITION I OL=4mA MIN IOVDD x 0.7 0 IOVDD x 0.7 0 0 TYP IOVDD IOVDD MAX 3.3 IOVDD x 0.3 3.3 IOVDD x 0.3 0.4 UNITS V V V V V
4. DOUT7-0, HBLK, VBLK, STROBE, DCLK
ITEM DOUT7-0, HIGH level output voltage HBLK, VBLK, STROBE, DCLK LOW level output voltage SYMBOL VOH DATA VOL DATA CONDITION IOH =-2mA I OL=2mA MIN 2.4 0 TYP IOVDD MAX 0.4 UNITS V V
5. RESET
ITEM HIGH level input voltage RESET LOW level input voltage HIGH level input current LOW level input current SYMBOL VIH RESET VIL RESET I IH RESET IIL RESET CONDITION VIN=GND VIN=IOVDD MIN IOVDD x 0.8 -10 -10 TYP MAX IOVDD x 0.2 10 10 UNITS V V A A
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TCM8240MD Ver 1.2 AC Characteristics (Ta=25 degree C, PVDD=IOVDD=2.8V, DVDD=1.6V)
1. EXTCLK
ITEM Clock frequesncy Rise time Fall time
Note; ALL values referred to VIHmin and VILmax levels.
SYMBOL f EXTCLK tr EXTCLK tf EXTCLK
MIN 6 -
TYP -
MAX 20 5 5
UNITS MHz ns ns
NOTE
*1
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TCM8240MD Ver 1.2
2. SCL, SDA
ITEM Clock frequency Low period SCL High period Rise time Fall time SDA Rise time Fall time SYMBOL f SCL tLOW SCL tHIGH SCL tr SCL tf SCL tr SDA tf SDA tHD STA tSU STA tHD DAT tSU DAT tSU STO tSP1 tSP2 Normal Wakeup from sleep mode MIN 0 1.3 0.6 0.6 0.6 0 100 0.6 0 0 MAX 400 300 300 300 300 50 20 UNITS kHz E s s s s s s s s s s s s s *1 NOTE
Hold time (repeated) START condition After this period, the first clock pulse is generated
Setup time for a repeated START condition Data hold time Data setup time Setup time for STOP condition Width of spike pulse
Note; * All values referred to VIHmin and VILmax levels.
SDA
tf tr tLOW tHD;STA tHD;DAT t SU;DAT tHIGH tf t HD;STA tSU;STA t SP tr
tBUF
SCL
tSU;STO
START
RE-START
STOP
START
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TCM8240MD Ver 1.2
3. DOUT7-0, DCLK, HBLK, VBLK
ITEM DCLK DOUT7-0, HBLK, VBLK Rise time Fall time Rise time Fall time SYMBOL tr DCLK tf DCLK tr DATA tf DATA tHD DATA tSU DATA MIN 10 10 MAX 6 6 6 6 UNITS s s s s s s NOTE
Data hold time Data setup time
Note; * All values referred to VOHmin and VOLmax levels.
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TCM8240MD Ver 1.2 Reference Drawing
Module shape is not finalized yet in detail. Following drawings are only reference for initial study.
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